| Paper: | DISPS-P3.1 | ||
| Session: | Design and Mapping Techniques for DSP Systems | ||
| Time: | Friday, May 19, 16:30 - 18:30 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Design of Programmable Signal Processors | ||
| Title: | An FPGA based coprocessor for cancer classification using nearest neighbour classifier | ||
| Authors: | Muhammad Atif Tahir, Ahmed Bouridane, Queen's University, Belfast, United Kingdom | ||
| Abstract: | This paper discusses the suitability of reconfigurable computing to speedup classification problems using Nearest Neighbour (1NN) classifier. 1NN classifier is widely used in the literature especially in real-time applications such as face recognition, on-line hand-written character recognition and medical applications where the performance enhancement in terms of speed is desirable. To evaluate the effectiveness of our implementation on Field Programmable Gate Arrays (FPGAs), experiments were carried out on two medical data sets. Results have shown that the classification accuracy is exactly same for both FPGAs and microprocessor based solutions with FPGA has superior speed performances. | ||
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