| Paper: | IMDSP-P5.7 | ||
| Session: | Image Coding | ||
| Time: | Wednesday, May 17, 10:00 - 12:00 | ||
| Presentation: | Poster | ||
| Topic: | Image and Multidimensional Signal Processing: Still Image Coding | ||
| Title: | Design and Implementation of Word-Level Embedded Block Coding Architecture in JPEG 2000 Decoder | ||
| Authors: | Yu-Wei Chang, Hung-Chi Fang, Chun-Chia Chen, Liang-Gee Chen, National Taiwan University, Taiwan | ||
| Abstract: | This paper presents a word-level decoding architecture of Embedded Block Coding (EBC) in JPEG~2000. This architecture decode one coefficient per cycle based on the proposed word-level decoding algorithm. This algorithm eliminates state variable memories by decoding all bit-planes in parallel. The proposed column-switching scan order overcomes intra bit-plane dependency and inter bit-plane dependency to enable parallel processing. Implementation results show the proposed architecture can decode 54 MSamples/s at 54 MHz, which can support HDTV 720p (1280x720, 4:2:2) decoding at 30 frames/sec in real time. | ||
©2018 Conference Management Services, Inc. -||- email: webmaster@icassp2006.org -||- Last updated Friday, August 17, 2012