| Paper: | DISPS-P3.8 | ||
| Session: | Design and Mapping Techniques for DSP Systems | ||
| Time: | Friday, May 19, 16:30 - 18:30 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | Single Cycle Nonlinear VLSI Cell for the ICA Algorithm | ||
| Authors: | Vijay Jain, University of South Florida, United States | ||
| Abstract: | This work is motivated by the desire to map the Independent Component Analysis (ICA) technique to a coarse-grain parallel-processing chip architecture. As in many other advanced DSP algorithms, the computation of such functions is pervasive in this algorithm. We discuss an efficient hardware approach to the computation of nonlinear functions for the ICA, some of which are compound or concatenated functions. All of the needed functions are regularized into a single efficient algorithm, and a new result is produced every cycle – in a pipelined mode – even for a different function every cycle. The underlying principle which makes the combined goals of high-speed and multi-functionality possible is significance-based polynomial interpolation of ROM tables. Very importantly, the paper uses a key formula for predicting and bounding the worst case arithmetic error. This theoretical result enables the designer to quickly select the architectural parameters without the expensive simulations, while guaranteeing the desired accuracy. | ||
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