| Paper: | DISPS-L2.6 | ||
| Session: | Efficient implementations of Communications and Coding Applications | ||
| Time: | Friday, May 19, 15:40 - 16:00 | ||
| Presentation: | Lecture | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | Distributed Architecture and Interconnection Scheme for Multiple Model Particle Filters | ||
| Authors: | Akshay Athalye, Sangjin Hong, Petar Djuric, Stony Brook University, United States | ||
| Abstract: | In this paper, we present a hardware architecture for a Sampling Importance Resampling Filter (SIRF) applied to systems with multiple interacting models. This filter outperforms traditional filters in practical scenarios due to superior abilities of the SIRFs in dealing with nonlinear and/or non-Gaussian models. Compared to existing approaches, our method does not require knowledge of model transition probabilities and keeps a constant number of particles per model at all times. This allows for a regular hardware structure with deterministic execution time. A highly scalable, parallel architecture consisting of distributed processing elements and a central unit is described. We propose an interconnection scheme and data exchange protocol using the concept of distributed resampling that greatly speeds up filter execution and drastically reduces the required interconnect to a single bus without causing any communication bottleneck. The proposed architecture is evaluated on a Xilinx FPGA platform for a multiple model target tracking application and its efficiency and salability is shown. | ||
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