| Paper: | DISPS-L2.3 | ||
| Session: | Efficient implementations of Communications and Coding Applications | ||
| Time: | Friday, May 19, 14:40 - 15:00 | ||
| Presentation: | Lecture | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | AN ENERGY EFFICIENT SUB-THRESHOLD BASEBAND PROCESSOR ARCHITECTURE FOR PULSED ULTRA-WIDEBAND COMMUNICATIONS | ||
| Authors: | Vivienne Sze, Raul Blazquez, Manish Bhardwaj, Anantha Chandrakasan, Massachusetts Institute of Technology, United States | ||
| Abstract: | This paper describes how parallelism in the digital baseband processor can reduce the energy required to receive ultra-wideband (UWB) packets. The supply voltage of the baseband is lowered so that the correlator operates near its minimum energy point resulting in a 68% energy reduction across the entire digital baseband. This optimum supply voltage occurs below the threshold voltage, placing the circuit in the sub-threshold region. The correlator and the rest of the baseband must be parallelized to maintain throughput at this reduced voltage. While sub-threshold operation is traditionally used for low energy, low frequency applications such as wrist-watches, this paper examines how sub-threshold operation can be applied to low energy, high performance applications. The correlators are further parallelized for a 31x reduction in the synchronization time, which along with duty-cycling, lowers the energy per packet by 43% for a 500 byte packet. Simulation results for a 100Mbps UWB baseband processor are described. | ||
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