| Paper: | DISPS-P1.10 | ||
| Session: | VLSI Architectures and Algorithms for Image and Video Processing | ||
| Time: | Tuesday, May 16, 14:00 - 16:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | Architecture for Hierarchical Block Motion Estimation using Variable Block Sizes | ||
| Authors: | Teahyung Lee, David V. Anderson, Georgia Institute of Technology, United States | ||
| Abstract: | In this paper, we propose a new architecture for hierarchical block motion estimation (HBME) algorithms using variable block sizes. The binary tree architecture (BTA) is well suited to HBME with constant block size because of the interdependence between computations in different levels of search. However, HBME algorithms based on variable block sizes can decrease the processing element (PE) utilization of BTA. The modified binary tree architecture (MBTA) presented here improves the PE utilization and area efficiency of BTA with low overhead for HBME algorithms using variable block sizes. We describe the architecture of MBTA and present the comparison of the performance with BTA for wavelet-based multi-resolution motion estimation (MRME) algorithms. | ||
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