| Paper: | DISPS-P1.11 | ||
| Session: | VLSI Architectures and Algorithms for Image and Video Processing | ||
| Time: | Tuesday, May 16, 14:00 - 16:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware for Image and Video Coding | ||
| Title: | ANALYSIS AND ARCHITECTURE DESIGN FOR MEMORY EFFICIENT PARALLEL EMBEDDED BLOCK CODING ARCHITECTURE IN JPEG 2000 | ||
| Authors: | Lien-Fei Chen, Tai-Lun Huang, Tzau-Min Chou, Yeong-Kang Lai, National Chung Hsing University, Taiwan | ||
| Abstract: | In this paper, a memory efficient parallel Embedded Block Coding (EBC) architecture with throughput enhancement in JPEG 2000 applications is proposed. In order to reduce the memory size, the memory-free algorithm for state variables in the context formation (CF) is proposed. The proposed algorithm eliminates the state variable memories by calculating three coding state variables on the fly. We also propose the stripe-column-based pass-parallel operation to perform three coding passes and four samples within the stripe-column concurrently. The FIFO architecture between the high throughput CF and the arithmetic encoder (AE) is also optimized by the pipelined sorter and the parallel-in parallel-out register file. Owing to the proposed high parallel CF, we propose a parallel and two-stage pipelined AE architecture to deal well with the context/decision (CX/D) pairs for three coding passes. The experimental results show that memory size of the proposed architecture is smaller than other familiar architectures, and the proposed architecture can process the lossless coding about 50MSamples/sec at 100-MHz. | ||
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