| Paper: | SPCOM-P1.9 | ||
| Session: | Coding and Compression | ||
| Time: | Tuesday, May 16, 10:30 - 12:30 | ||
| Presentation: | Poster | ||
| Topic: | Signal Processing for Communication: Applications involving signal processing for communication | ||
| Title: | Pipelined Block-Serial Decoder Architecture for Structured LDPC Codes. | ||
| Authors: | Tejas Bhatt, Vishwas Sundaramurthy, Victor J. Stolpman, Dennis McCain, Nokia Research Center, United States | ||
| Abstract: | We present a pipelined block-serial decoder architecture for structured LDPC Codes, implementing the layered-mode belief-propagation. We introduce the concept of LLR-update and mirror memory to enforce a pipelined decoding schedule. The pipelined architecture improves the latency of the LDPC decoder by about 2x-3x and has negligible performance loss when implemented with clever layer scheduling. We also present a low-complexity check-node architecture suitable for block-serial processing and utilize the properties of the min approximation to significantly reduce the memory requirement. The proposed architecture is suitable for mobile devices with data-rates of tens of mbps. | ||
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