| Paper: | DISPS-P2.2 | ||
| Session: | Hardware and Software Implementations of DSP Systems | ||
| Time: | Thursday, May 18, 16:30 - 18:30 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | A High-Speed Fully Programmable VLSI Decoder for Regular Low Density Parity Check (LDPC) Codes | ||
| Authors: | Euncheol Kim, NIkhil Jayakumar, Pankaj Bhagwat, Anand Selvarathinam, Gwan Choi, Sunil Khatri, Texas A&M University, United States | ||
| Abstract: | This paper presents a single-chip VLSI implementation of an LDPC decoder that can achieve 2.4 Gbps throughput yet permits real-time configuration of (1) rate, (2) code length, and (3) the parity check matrix pattern. This decoder can be programmed in the field, much like a Field Programmable Gate Array (FPGA). However, our hardware design is customized specifically for the task of decoding LDPC codes. We describe the architectural, circuit-level and layout-level details of our implementation. Our design can handle variable rate codes of length up to 1024, and is implemented in a 0.1?m VLSI fabrication process. Our design has a die size of 12mm by 8mm and a power consumption of 7W. This implementation can easily be modified to handle longer codes in a partially parallel manner, and allow for on-the-fly reconfigurability of the code. We anticipate that our implementation can be used as a means to study LDPC code performance, as an alternative to software simulation or emulation. | ||
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