| Paper: | DISPS-P1.5 | ||
| Session: | VLSI Architectures and Algorithms for Image and Video Processing | ||
| Time: | Tuesday, May 16, 14:00 - 16:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | EFFICIENT VLSI ARCHITECTURE OF LIFTING-BASED WAVELET PACKET TRANSFORM FOR AUDIO AND SPEECH APPLICATIONS | ||
| Authors: | Chao Wang, Woon Seng Gan, Nanyang Technological University, Singapore | ||
| Abstract: | This paper presents an efficient VLSI architecture for discrete wavelet packet transform (DWPT). By exploiting the in-place nature of the DWPT algorithm, this architecture has an efficient pipeline structure to implement high-throughput processing. Folded architecture for lifting-based wavelet filters is proposed to compute wavelet butterflies in different groups simultaneously, at each decomposition level. Internal pipelining and by-pass mode are employed on each processing element to increase computation throughput and provide easy configuration for arbitrary decomposition, respectively. According to the comparison results, our proposed VLSI architecture is more efficient than previous proposed architectures in terms of arithmetic operations, storage requirement, and throughput. | ||
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