| Paper: | DISPS-L2.1 | ||
| Session: | Efficient implementations of Communications and Coding Applications | ||
| Time: | Friday, May 19, 14:00 - 14:20 | ||
| Presentation: | Lecture | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware for Image and Video Coding | ||
| Title: | Architecture Design of Low Power Integer Motion Estimation for H.264/AVC | ||
| Authors: | Tung-Chien Chen, Yu-Han Chen, Sung-Fang Tsai, Liang-Gee Chen, National Taiwan University, Taiwan | ||
| Abstract: | In motion estimation, fast algorithms usually lead to the irregular searching flow, and the power reduction in architecture level is constrained for poor data reuse (DR). In this paper, a parallel IME hardware for H.264/AVC is proposed to well combine the techniques in algorithm and architecture levels. The ``2-D SAD Tree" is adopted to support intra- and inter-candidate DR for the content-adaptive parallel-VBS four step search algorithm. The ladder-shaped reference data arrangement is proposed to supprot DR in both horizontal and vertical directions, while the advanced searching flow is applied to reduce the latency cycles. After these two techniques, 77.6% power of search window SRAMs can be reduced. According to the implementation result, in ultra low power mode, only 1.424 mW is required for realtime encoding CIF 30fps videos with 13.5 MHz operation frequency. | ||
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