| Paper: | DISPS-P1.6 | ||
| Session: | VLSI Architectures and Algorithms for Image and Video Processing | ||
| Time: | Tuesday, May 16, 14:00 - 16:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | AREA-EFFICIENT NEDA ARCHITECTURE FOR THE 1-D DCT/IDCT | ||
| Authors: | Archana Chidanandan, Rose-Hulman Institute of Technology, United States; Magdy Bayoumi, University of Louisiana at Lafayette, United States | ||
| Abstract: | New Distributed Arithmetic has been been applied to the 1-D DCT to produce a low power, high throughput architecture. In this paper, we apply NEDA to the even-odd decomposition matrices of the 8 x 8 forward and inverse DCT. We show that, with the proposed approach, the number of adders required for the adder array for the forward DCT and the inverse DCT is fewer than required if NEDA is applied directly to the 8 x 8 DCT and IDCT matrices. This reduction will result in power savings, without decreasing the throughput. Also, for the inverse DCT, the number of adder stages is reduced, resulting in faster decoding. | ||
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