| Paper: | DISPS-P1.9 | ||
| Session: | VLSI Architectures and Algorithms for Image and Video Processing | ||
| Time: | Tuesday, May 16, 14:00 - 16:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Fast Algorithms | ||
| Title: | Low Power CORDIC IP Core Implementation | ||
| Authors: | Ruiqi Zhang, Institute for System Level Integration, United Kingdom; Jong Hun Han, Ahmet T. Erdogan, Tughrul Arslan, University of Edinburgh, United Kingdom | ||
| Abstract: | There is a high demand for low power and efficient implementation of complex arithmetic operations in many Digital Signal Processing (DSP) algorithms. The COordinate Rotation DIgital Computer (CORDIC) algorithm which was first introduced by Volder[1] is suitable to be implemented in DSP systems since its calculation for complex arithmetic is simple and elegant. Besides, design complexity and power consumption can be reduced since the CORDIC algorithm avoids using multiplications. This paper presents three CORDIC IP cores which were implemented using a new CORDIC algorithm. Each of them has one or more distinctive performances in terms of power, area, speed and flexibility due to their different architectures. | ||
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