| Paper: | DISPS-P1.1 | ||
| Session: | VLSI Architectures and Algorithms for Image and Video Processing | ||
| Time: | Tuesday, May 16, 14:00 - 16:00 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Hardware, Software, and Algorithm Tradeoffs and Integration | ||
| Title: | Line Buffer Wordlength Analysis for Line-Based 2-D DWT | ||
| Authors: | Chih-Chi Cheng, Chao-Tsung Huang, Jing-Ying Chang, Liang-Gee Chen, National Taiwan University, Taiwan | ||
| Abstract: | The on-chip line buffer dominates the total area and power of line-based 2-D DWT. Therefore, the line buffer wordlength has to be carefully designed to maintain the quality level due to the dynamic range growing and the round-off errors. In this paper, a complete analysis methodology is proposed to derive the required wordlength of line buffer given the desired quality level of reconstructed image. The proposed methodology can guarantee to avoid overflow of coefficients, and the difference between predicted and experimental quality level is averagely 0.06 dB in terms of PSNR. | ||
©2018 Conference Management Services, Inc. -||- email: webmaster@icassp2006.org -||- Last updated Friday, August 17, 2012