| Paper: | DISPS-P3.7 | ||
| Session: | Design and Mapping Techniques for DSP Systems | ||
| Time: | Friday, May 19, 16:30 - 18:30 | ||
| Presentation: | Poster | ||
| Topic: | Design and Implementation of Signal Processing Systems: Custom Processors, Architectures, and VLSI Hardware | ||
| Title: | EFFICIENT CORDIC DESIGNS FOR MULTI-MODE OFDM FFT | ||
| Authors: | Cheng-Ying Yu, Sau-Gee Chen, Jen-Chuan Chih, National Chiao Tung University, Taiwan | ||
| Abstract: | In this paper, we propose a new CORDIC algorithm and architectures which can generate close-to-optimum rotation sequences easily with small lookup table sizes. This new design is particularly suitable for the applications of adjust-able-length FFT. In all, the required number of shift-and-add operations for micro-rotations and scale-factor compen-sations is only n/2, where n is the output precision. For de-sign verification, we synthesized both serial and pipelined architectures, by using Synopsys Design Complier based on UMC 0.18 , 1P6M CMOS technology. The synthesized 16-bit pipelined FFT PE runs at 222MHz, with a total gate count of 89263 and a low-power consumption of 26.75 mW. It meets the FFT speed requirements of most OFDM-based communication systems, including DAB, DVB, 802.16 and VDSL. Compared with a conventional multiplier-based FFT PE and the existing CORDIC-based FFT PE’s, the proposed designs has better performances in terms of area, speed and power consumption.. | ||
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