DISPS-P1: VLSI Architectures and Algorithms for Image and Video Processing |
| Session Type: Poster |
| Time: Tuesday, May 16, 14:00 - 16:00 |
| Location: Poster Area 1 |
| Chair: Liang-Gee Chen, National Taiwan University |
| DISPS-P1.1: LINE BUFFER WORDLENGTH ANALYSIS FOR LINE-BASED 2-D DWT |
| Chih-Chi Cheng, Chao-Tsung Huang, Jing-Ying Chang, Liang-Gee Chen, National Taiwan University, Taiwan |
| DISPS-P1.2: OPTIMIZATION AND IMPLEMENTATION ON FPGA OF THE DCT/IDCT ALGORITHM |
| Ahmed Ben atitallah, Patrice Kadionik, IXL-ENSEIRB, France; Fahmi Ghozzi, LETI-ENIS, Tunisia; Patrice Nouel, IXL-ENSEIRB, France; Nouri Masmoudi, LETI-ENIS, Tunisia; Philippe Marchegay, IXL-ENSEIRB, France |
| DISPS-P1.3: LOW COMPLEXITY ARCHITECTURE DESIGN OF H.264 PREDICTIVE PIXEL COMPENSATOR FOR HDTV APPLICATION |
| Jia-Wei Chen, Chien-Chang Lin, Jiun-In Guo, Jinn-Shyan Wang, National Chung Cheng University, Taiwan |
| DISPS-P1.4: STRUCTURALLY ORTHOGONAL FINITE PRECISION IMPLEMENTATION OF THE EIGHT POINT DCT |
| Marek Parfieniuk, Alexander Petrovsky, Bialystok Technical University, Poland |
| DISPS-P1.5: EFFICIENT VLSI ARCHITECTURE OF LIFTING-BASED WAVELET PACKET TRANSFORM FOR AUDIO AND SPEECH APPLICATIONS |
| Chao Wang, Woon Seng Gan, Nanyang Technological University, Singapore |
| DISPS-P1.6: AREA-EFFICIENT NEDA ARCHITECTURE FOR THE 1-D DCT/IDCT |
| Archana Chidanandan, Rose-Hulman Institute of Technology, United States; Magdy Bayoumi, University of Louisiana at Lafayette, United States |
| DISPS-P1.7: MATRIX FACTORIZATION FOR FAST DCT ALGORITHMS |
| Wenjia Yuan, Peking University, China; Pengwei Hao, Queen Mary, University of London, United Kingdom; Chao Xu, Peking University, China |
| DISPS-P1.8: NEAR-OPTIMAL LOW-COST DISTORTION ESTIMATION TECHNIQUE FOR JPEG2000 ENCODER |
| Amit Kumar Gupta, David Taubman, Saeid Nooshabadi, University of New South Wales, Australia |
| DISPS-P1.9: LOW POWER CORDIC IP CORE IMPLEMENTATION |
| Ruiqi Zhang, Institute for System Level Integration, United Kingdom; Jong Hun Han, Ahmet T. Erdogan, Tughrul Arslan, University of Edinburgh, United Kingdom |
| DISPS-P1.10: ARCHITECTURE FOR HIERARCHICAL BLOCK MOTION ESTIMATION USING VARIABLE BLOCK SIZES |
| Teahyung Lee, David V. Anderson, Georgia Institute of Technology, United States |
| DISPS-P1.11: ANALYSIS AND ARCHITECTURE DESIGN FOR MEMORY EFFICIENT PARALLEL EMBEDDED BLOCK CODING ARCHITECTURE IN JPEG 2000 |
| Lien-Fei Chen, Tai-Lun Huang, Tzau-Min Chou, Yeong-Kang Lai, National Chung Hsing University, Taiwan |
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